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VHDL Coding Styles and Methodologies, by Ben Cohen
PDF Download VHDL Coding Styles and Methodologies, by Ben Cohen
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VHDL Coding Styles and Methodologies, Edition is a follow up book to the first edition of same book and to VHDL Answers to Frequently Asked Questions, first and second editions. This book was originally written as a teaching tool for a VHDL training course. The author began writing the book because he could not find a practical and easy to read book that gave in depth coverage of both, the language and coding methodologies. This edition provides practical information on reusable software methodologies for the design of bus functional models for testbenches. It also provides guidelines in the use of VHDL for synthesis. All VHDL code described in the book is on a companion CD. The CD also includes the GNU toolsuite with EMACS language sensitive editor (with VHDL, Verilog, and other language templates), and TSHELL tools that emulate a Unix shell. Model Technology graciously included a timed evaluation version of ModelSim, a recognized industry standard VHDL/Verilog compiler and simulator that supports easy viewing of the models under analysis, along with many debug features. In addition, Synplicity included a timed version of Synplify, a very efficient, user friendly and easy to use FPGA synthesis tool. Synplify provides a user both the RTL and gate level views of the synthesized model, and a performance report of the design. Optimization mechanisms are provided in the tool.
- Sales Rank: #1794009 in Books
- Brand: Brand: Springer
- Published on: 1999-03-31
- Original language: English
- Number of items: 1
- Dimensions: 10.00" h x 1.13" w x 7.01" l, 2.16 pounds
- Binding: Hardcover
- 455 pages
- Used Book in Good Condition
About the Author
Ben Cohenis the co-founder of Ben and Jerry s Ice Cream and the Head Stamper with StampStampede.org.He encourages everyone to join him inthe joy ofstamping money out of politics at StampStamede.org.
Most helpful customer reviews
12 of 12 people found the following review helpful.
Very Difficult to Read
By Julius Caesar
As the title said, this book has a lot of good examples on how to write VHDL code with good coding styles. Most of the good coding style tips in the book make sense and I use it in my work. However, I don't think this is a good book to learn VHDL. The syntax is explained in the same style as the VHDL Language Reference Manual, which is very dry. For example: the author explained the syntax of for loop like this: loop_statement ::= [loop_label][iteraction_scheme] loop sequence_of_statements end loop [loop_label]. I learned some VHDL constructs from this book but they are not very clear. After finished reading the book, I still feel something missing and I need to refer to other VHDL books to fill up the gap. The author also spent only a few pages on synthesis and the index is poorly organized. With all of these and combined with its ridiculous price, I would recommend to borrow the book from library if you want some tips on good coding styles. But I won't recommend to buy it if you want to learn basic VHDL, because the book is no good for that purpose.
9 of 9 people found the following review helpful.
Best practical book I have read yet.
By A Customer
This is an excellent book for the practicing engineer who wants a real world example. The book has many examples of code which will compile and work. In addition it has recommendations on best practices ( 2 thumbs up) and worst practices (2 thumbs down) with a rational for why you would want to follow the recommended practice. It also makes clear distinction between sythesizable code, and behavioral code. Compared with the other books which are heavy on the language semantics (and examples that won't compile) this is a much more usable book. The hardware desiner will find this to be the best book they have.
11 of 12 people found the following review helpful.
What a book!
By L. Riggs
This book has just become my number one book to recommend to the students of the VHDL classes that I teach. It is very well written and the book is loaded with VHDL examples demonstrating the various constructs, statements and issues. In example 5.5.1.2, the author does the best job I have ever seen of explaining the difficult subject of "Projected Output". The subjects are frequently associated to the specifications found in the Language Reference Manual. When there is a linking issue between two or more design elements, the linking is clearly demonstrated with examples. The only negative is that the author spends far too much time and book space describing ways to "Enhance Readibility" or documenting your design--which is always a personal preference. But still, a five star book.
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